APaga1
New Contributor
5 years agoTiming failure in the SDRAM of the NIOS Simple Socket Server
Hello,
I am trying to use NIOS II Simple Socket Server design template where I have integrated our custom IP in the ethernet standard main system qsys file. When we are trying to compile, we are getting timing violations in the SDRAM that is present in the ethernet standard main system qsys. As this is something from the Intel, I am unable to interpret the nodes that I have located through the Timing analyzer GUI. I have used afi_clock as input clocks to our customized IP that I have integrated with NIOS. Kindly help. I am attaching some screenshots. The board that we are using is Cyclone V GT.