Honored Contributor
Honored ContributorAll of those warnings you can ignore except the one about the memory being synthesized away (not sure it's safe to ignore since I don't see the culprit).
One suggestion, hook up the JTAG Debug Module reset to all of the reset inputs in your system so that the external reset or the debugger can trigger a reset. When I download code I normally enable the downloader to reset my system so that I know it'll be in a known state when the code starts executing. The only other thing that I can think of is did you make sure to assign your clock and PIO signals to I/O? If you didn't assign those Quartus will normally figure out the clock for you and hook it up to an FPGA clock pin (doesn't necessarily mean that clock pin is connected to a valid clock on your board though). The PIO it would just route those signals to wherever it can to improve the timing of your design. I've seen this cause problems for others in the past since having inputs/outputs randomly routed can cause all kinds of nasty stuff to happen. Also I would hook up the reset pin in your design after you get the code downloading working correctly. I've seen others design themselves into a corner by omitting resets in their design so I would just get into a habit of always including it.
