LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro

Hi dim1​ 

dim1 wrote:

In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3

Yes, you are correct that it is the same problem. Reassure that it is resolved in Quartus Prime 26.1.1 Pro.
(Your post arrived first, while I am still preparing the KDB)

dim1 wrote:

Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?

Not exactly.

1. In the linked post, the user is connecting a 4GB 32-bit processor address map to a larger EMIF, such as 8GB. Minus 2 GB for other peripherals, you are left with 2GB processor address map to 8GB EMIF. 
   So, they need to connect a Address Span Extender IP between the processor & EMIF IP.
2. However, the Address Span Extender IP is still affected by this "no EMIF" issue in BSP Linker.
   So, the workaround is to manually add the EMIF + ASE into BSP Linker.

They are two separate issues in a single post.


For your design,

1. Your EMIF is able to fit inside the remaining 2GB 32-bit processor address map. No ASE IP is needed here. 
2. The EMIF IP is affected by the "no EMIF" issue in the BSP Linker. Currently, the workaround is to manually add the EMIF into BSP Linker.
   Reference (Replace ASE IP as EMIF IP, and follow the same steps): 

   https://docs.altera.com/r/docs/726952/26.1/nios-v-embedded-processor-design-handbook/defining-address-span-extender-linker-memory-device 

Regards,
Liang Yu

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