timing_error_for_pll_afi_clock_on_ddr3_ip_controller

Hi Team,

I am checking the design with ddr3 interface, nios processor and other interfaces also in cyclone v gx device(5CGXFC5C6F27C7). I have given memory clock as 400 Mhz(ddr3 ip parameter setting) and uses afi_clock(200 Mhz) to connect the clock of other interfaces.

pll_clock of ddr interface is 50 Mhz. connected from the osciallator in the board.

Nios processor also connected with afi clock only (200 Mhz)

For this design , i am getting pll_afi_clock setup time violation.

i have attached the timing report.

PLease give solution for this.