Hi, I am trying to interface with the SDM via the Mailbox Client IP. I have created my own AVALON like interface to communicate with the mailbox client. I have been able to successfully read the C...
Hi William,
I have tested the command on v19.1 Pro and it seems like there is no problem in executing it. It seems to me that it might be due to command execution flow issue. I have included the flow to execute the command in TCL using system console:
global omp b0 b1 b2 b3 b4 b5 b6 b7 b8
#writing the command header (Get_IDCODE)
master_write_32 $omp $b1 0x00000010
#Read ISR (Expect to get 0x3)
set ISR [master_read_32 $omp $b8 1]
while {$ISR != 0x00000003} {
puts "ISR is not ready yet!"
set ISR [master_read_32 $omp $b8 1]
}
#Read Response FIFO fill level, EOP and SOP (Expect to get 0x9) (optional)
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
while {$SOP_EOP_FIFO != 0x00000009} {
puts "SOP_EOP_FIFO is not ready yet!"
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
}
#read offset 5 for the first packet of data (Expect to get 0x1000)
master_read_32 $omp $b5 1
#Read Response FIFO fill level, EOP and SOP (Expect to get 0x6) (optional)
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
while {$SOP_EOP_FIFO != 0x00000006} {
puts "SOP_EOP_FIFO is not ready yet!"
set SOP_EOP_FIFO [master_read_32 $omp $b6 1]
}
#read offset 5 again to retrieve the response argument (in this case, this command only has one response argument, which is the IDCODE)
master_read_32 $omp $b5 1
Hope it helps.
Thanks,
YL
Hi,
I was able to figure out my problem. I was given AN 891, Using the Reset Release Intel Stratix 10 FPGA IP.
I didn’t change anything in my code except connected up this block to my reset signals and now I see 0x3h as my response in the ISR.
Thank you,
--Will
Hi,
I have run into a related issue with the mailbox client. I am able to perform the following commands successfully.
0x0 NOP
0x10 GET_IDCODE
0x12 GET_CHIPID
0x13 GET_USERCODE.
0x4 CONFIG_STATUS
I have however unable to perform either of the following 2 commands.
0x5c RSU_IMAGE_UPDATE
0x5b RSU_STATUS
In both cases, I get the response of 0x1 in the response header which means either INVALID_COMMAND or in the case of RSU_IMAGE_UPDATE, it “Returns non-zero response if the device is already processing a configuration.”
I don’t know what that means exactly. Is the SDM still talking to the active serial x4 device and I can communicate with it? I am running my image on the fpga with no issue, so I would think that I should be able to communicate with the device to send a reconfig command.
What I am trying to do is to have the fpga load the default image, and then I want to reconfigure the fpga to load a different image at an offset.
FYI: When I ran the CONF_STATUS command, I received the following results:
Word 0: 0x0
Word1: 0x0
Word 2:0xC000000b (nStatus & nConfig are ‘1’, MSEL is “001”, The other bit ‘1’ @ location 3 is reserved, so I don’t know what that means.)
Word 3: 0xc
Word 4 0x0
Word 5: 0x0
Any help / guidance would be appreciated.
--Will
Occasional Contributor
