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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
5 months ago
Solved

Simulating L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express using Questa

I'm following the user guide L-Tile and H-Tile Avalon MM+ Intel FPGA IP for PCI Express and using Questa Intel FPGA Edition to simulate. This is for Quartus Prime Design Suite 23.4.

I followed the procedure to generate a test design using Quartus Prime Pro, and I changed the working directory to the design/pcie_design_tb/pcie_design_tb/sim/mentor/

However on page 16 where it says I should invoke vsim which it said brings up a console where I can run the following commands, which it lists as do msim_setup.tcl then ld_debug and run -all

However when I invoke vsim, it expects me to put in the testbench design. Without this it complains that "No Design Loaded!" and it wont run. Or I will try the ld_debug and run -all it will try to compile with over 2500 warnings and one fatal error saying no design loaded.

Not sure if this is an error in the user guide. The transcript window is used to input paramaters, not by invoking vsim.

I'm using the DMA design.

Can someone assist me step by step on how I can sucessfully compile this design?

Pcie
  • RongY_altera's avatar
    RongY_altera
    4 months ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong


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  • RHobb's avatar
    RHobb
    Icon for Occasional Contributor rankOccasional Contributor
    4 months ago

    Sorry for the delay.

    The problem was with my Windows install, it has a space in a directory that has all my config data for all my programs. I ported the design over to CentOS 10, the latest update. It compiled in QuestaSim, took over 8 hours to simulate then failed. I used the design you sent me. I could not see any simulation waveforms.

    Will try again.

    If you don't mind, can you please append the WLF data? Once your simulation succeeds, it should post a message and ending the simulation run. I'm interested in the waveform data which you can save from the File menu. I can at least load this data in the advent there is another failure.

    Thank you

  • RHobb's avatar
    RHobb
    Icon for Occasional Contributor rankOccasional Contributor
    4 months ago

    Solved!

    But there are some points I want addressed.

    So everything worked in CentOS (10.0). I compiled the design for the PCI Express 3.0 x8 using the standard MM option, the generated design example did compile but it ended up failing because there was no stimulus, so it ran until 4 seconds and quit. (took 8 hours to complete)

    I then ran the other option, the PCI Express 3.0 x 16 (MM+) which automatically downtrains to x8, in the IP Generation dialogue box it does give you the option to have Intel BFM to apply, so I did that, compiled in QuestaSim and it ran to completion, everything worked.

    So why doesn't the User Manual explain if you run the standard x8 option that you have to supply your own testbench stimulus? And why doesn't the IP editor allow you to apply the Intel BFM for just the x8 option?

    In regards to switching to CentOS and disregarding my Windows problem, I feel like Quartus should be able to recognize spaces between names in the user path, and all this confusion could have been resolved and I could have proceeded with the Windows environment. The space between "Valued Customer" in my user downloaded configuration path that Quartus used DID created problems. I made sure to avoid any spaces during my CentOS installation and used short paths.

    Thanks for all the help and I hope this helps others out.

  • RongY_altera's avatar
    RongY_altera
    Icon for Contributor rankContributor
    4 months ago

    Thanks for the sharing of your conclusion and findings.


    You're right. The simulation of S10 PCIe AVMM example design has problem which reports "FAILURE: Simulation stopped due to Fatal error!". After checked, the same issue exists in Q25.1 Pro as well. This is a bug that we need to fix.


    Regards,

    Rong