Honored ContributorHello everyone!
I am working with a Stratix III EP3SE260F1152C3 FPGA doing my PFC (final career project) I need to generate a shift register using MLAB memory but Quartus II MegaWizard Plug-in Manager only allows to use 8LUT. How can I obtain my aim?:confused: Thank you very much!
Honored Contributorit can be a bit of a pain, but you can get an MLAB to have 0 read latency
Honored ContributorHonored ContributorI think it's a kind of misunderstanding. Some posters wanted a shift register with variable tap position and granularity of one. As altshift_taps is restricted to tap distances >= 3, using a threefold clock is an option to implement the function with altshift_taps though. A way of putting the cart before the horse.
Instead you'd ask, what's a suitable FPGA hardware the function can be mapped to, how can it be effectively coded? altshift_taps apparently isn't in this case.Honored Contributor99% of altshift_taps are used as a single shift-register with only one tap point. I would also say 90-95% of altshift_taps are just inferred by synthesis, i.e. if you create a shift-register in your code you'll see altshift_taps inferred if you look through the synthesis reports(actually, the best place is the Fitter Report -> Resource Utilization -> RAM Summary, copy all the names to a text file and search on "altshift").
Honored ContributorThanks for answer. You saved my time.
In fact my problem was in the clock enable. Now it works as expected. I use this as a single shift register like 99% ;-) I have to use the megawizard and instantiate this altshift_taps. Quartus synthesis doesn't recognize my VHDL piece of code as a shift register : 21 * (256 sample * 24 bit wide), even if I forget the asynchronous clear, registerd my inpout and ouput signals, force Quartus to enable "logic to ram" and RAM associated options. In this case, Quartus takes half an hour to synthesis and takes many many many DFF.
