PCIe w/ Avalon ST: Equivalent of ko_cpl_spc_vc0?

Hi Matthias

Thank you for the very detailed answer. I can see the k0_cpl_spc_vc0 bus in simulation, so that will help with one part of the problem. Also, the Xilinx UG517 is very useful, and provides more detail than the Altera PCIe User Guide.

However, I think the algorithms in UG517 assume that the user application has access to the values for CPLH and CPLD credits on the receive side. When I use the test_in bus on the PCIe hard macro to drive the receive credits on the test_out bus (ie test_in[11:8] == 6), the values I see on test_out are 64'h0361_6832 and 64'h0351_6832. According to PCIe User Guide Version 9.1 Table B-9 the CPLH and CPLD credits are at bits 43:36 and 55:44 respectively, and these are always 0, indicating infinite credits, which is in agreement with the PCIe spec. When I do get receive buffer overflow, the PCIe hard macro just swallows the RCB, with no indication on any signals that I can see. Even the specific receiver overflow bits on the test_out bus (selectable with other values of test_in[11:8]) don't seem to toggle.

I'm currently implementing the LIMIT_FC algorithm, and unless I'm wrong about the CPLH/CPLD credits, I think this is my only option, though I'd be glad to find out that I'm wrong.

Brendan