Occasional ContributorIssue with BSP Creation for Nios-V/m Using LPDDR4 on Agilex-5 (Quartus 24.1 & 24.3.1)
Hello,
We are encountering an issue while creating a BSP for the Nios-V/m targeting Agilex-5 using LPDDR4 as the processor memory. We have attempted this using Quartus 24.1 and 24.3.1 but faced the same problem in both versions.
Setup Attempted:
- We connected the data and instruction interfaces of Nios-V/m to the External Memory Interfaces (EMIF) IP directly.
- We also tried routing them through the Address Span Extender Intel FPGA IP before connecting to the EMIF.
- In both cases, the memory interface is detected correctly under the "Vectors" section as the "Reset Agent" in the parameters editor of the Nios-V/m.
Issue:
When creating the BSP, we receive the following errors:
[Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]"
[Error] CPU "intel_niosv_m" has no memories connected to its Avalon host(s)
[Error] CPU "intel_niosv_m" reset memory "emif_2b" has no matching memory region.
The instance name of the EMIF IP core in our design is "emif_2b". The last line of the message is different if we use "Address Span Extender Intel FPGA IP". Additionally, we cannot manually add the required memory regions in the BSP Link Script within the BSP Editor, as the "Memory Region" field remains empty when attempting to add a region.
Additional Observations:
- This issue did not occur with Nios-V/m on Agilex-7 using Quartus 23.4, where the Address Span Extender IP was correctly assigned for different memory regions in BSP. In this case, we were using a DDR4 Memory.
- The issue also does not occur when using On-Chip RAM as the processor memory.
- A possible difference is that in Quartus 23.4, the EMIF IP’s memory interface is "Avalon Memory Mapped Agent", whereas in Quartus 24.1 and 24.3.1, it is "AXI4 Subordinate".
- The type of Nios-V/m data and instruction buses is "AXI4Lite Manager" in both setups (Agilex-7 with Quartus 23.4 and Agilex-5 with Quartus 24.1/24.3.1).
Request for Assistance:
Could you provide the correct procedure for using LPDDR4 memory as the memory of Nios-V/m with the corresponding EMIF IP in Agilex-5 FPGAs?
At this moment, we are particularly interested in the correct setup for Quartus 24.1 with "External Memory Interfaces (EMIF) IP" which is no longer available in Quartus 24.3.1. However, we also tested "External Memory Interfaces (EMIF) IP - LPDDR4" in Quartus 24.3.1 with a similar outcome.
Thanks in advance for your help!
