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aucamera1's avatar
aucamera1
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25 days ago

GTS SDI II IP Core...what is the tx_vid_clkout frequency

I'm using an Agelix 5 (the Altera development board) with Quartus Pro 25.3.1 w/patch 1.02.

i'm trying to set-up the GTS SDI II IP Core (version 2.3.0)

on the Main screen, the only configurable values are:

  • Video Standard = HD-SDI
  • Direction = Transmitter
  • Insert payload ID = off
  • SDI_II wrapper = Both BASE and PHY

everything else is grayed out.

I have connected the tx_pll_refclk to the 148.5MHz input.   I do see the tx_pll_locked signal behave as expected and it does lock.

the problem is when I look at the tx_vid_clkout signal its 58.3MHz.  I expected it to be 74.25MHz.

I'm somewhat confused as to whether tx_pll_refclk should be 148.5MHz or 74.25MHz, but if the 148.5 is wrong then I would have expected tx_vid_clkout to be twice, not a somewhat random value of 58.3MHz.

when I reconfigured the IP core for 3G-SDI, the tx_vid_clkout frequency doubled to 116MHz.  The doubling would be what I expected, but still a wrong frequency.

i'm not sure what i'm setting wrong and why i'm getting a clkout of 58.3MHz

Video

20 Replies

  • aucamera1's avatar
    aucamera1
    Icon for New Contributor rankNew Contributor
    24 days ago

    I'm checking the frequency via a clock measuring logic circuit I have.  I have several clocks I'm doing this with.  

    I'm using the Agilex 5 FPGA E-Series 065B Premium Development Kit

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      21 days ago

      Hi aucamera1 ,

      Your configuration and 148.5 MHz refclk are likely fine. The ~58.3 MHz (HD) and ~116 MHz (3G) clocks indicate the SDI II IP selected a wider internal word width (effectively ~25 bits), 
      which is expected behavior when the “Both BASE and PHY” wrapper auto-manages transceiver constraints on Agilex 5. 
      If you need tx_vid_clkout = 74.25 MHz, regenerate the IP so you can select 20/40-bit widths, or synthesize 74.25 MHz externally and re-time.
      Your numbers line up with the SDI II IP auto-selecting a wider internal parallel word width than the “classic” 20-bit/40-bit path. In the SDI II transmitter, the user video clock (tx_vid_clkout) is essentially:

      • tx_vid_clkout ≈ serial line rate / internal TX parallel word width

      If the IP uses:

      • 20-bit width (HD) → 1.485/20 = 74.25 MHz
      • 25-bit width (HD) → 1.485/25 = 59.4 MHz
      • 40-bit width (3G) → 2.97/40 = 74.25 MHz
      • 25-bit width (3G) → 2.97/25 = 118.8 MHz
      • 50-bit width (3G) → 2.97/50 = 59.4 MHz

      Your measurements:

      • ~58.3 MHz in HD mode is close to the ~59.4 MHz expected for a 25-bit path (allowing for measurement tolerance and fractional-rate variants).

      Regards,
      Wincent

      • aucamera1's avatar
        aucamera1
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        21 days ago

        Hi Wincent_Altera​ ,

        Sorry, but i'm a bit confused by your answer.  There is no 25-bit HD-SDI setting.  The bit width is set by the Video Standard (except for SD-SDI which can be selectable 10 or 20-bits, but not sure its even supported for Agelix 5).  So if you're saying 25-bits is being selected, how do I force it back to 20?

        thanks,   -rob

         

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    24 days ago

    Hi aucamera1 ,


    Just want to confirm, how you check the frequency ?
    Through analyzer or oscilloscope ? I might need to try and see if I can replicate your issue in my place.
    Which devkit you are using ? Modular or Premium devkit ?

    Regards,

    Wincent

    • aucamera1's avatar
      aucamera1
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      24 days ago

      I just went back and pulled the tx_vid_clkout onto a user IO pin and verified it is 58MHz with an o'scope.