Altera_Forum
Honored Contributor
8 years agoFFT megacore IP (source_sop is asserted for 2 cycles, sink_ready random deasserts)
Hi,
I'm having a couple of problems with the FFT IP core in variable streaming mode. When outputting the FFT transform results, the source_sop signal is asserted for two cycles instead of one. I thought this might be related to my sink_sop and eop signals, but these both pulse for one cycle only. My flow controller/FSM generally pulses sop, streams data of whatever size, pulses eop, then sets sink_valid to 0 for 1 cycle, which I use to give the core time to receive the new FFT size value. I believe this works for FFT sizes of 8, despite the SOP pulse width weirdness. However, when my testbench changes the FFT input size to 16, the sink_ready signal is de-asserted (perhaps I should just pause while I wait longer for the signal to be asserted again? I will try this in this meantime ). Due to this, the rest of my results are incorrect, and source error shows '11'. I believe this is due to the FFT internals, as my sink_error stays '00' for the entire time. I did some googling and found that people discovered a bug in the FFT core DSP with the ready signal deasserting, but that was a while ago (2008 IIRC), so I assume the problem fixed. I have attached a .png of my modelsim waveform. I am still learning Quartus etc, so am not sure what files are required to allow simulation. If anyone that can help requires extra waveform files etc, let me know and I will attach them. Thanks for taking your time to read this, I find this forum help invaluable. ap29