Occasional ContributorExploring why GSFI IP Core repeats sending command and address for each 4-byte data in Page Program
Dear Intel Support Team,
We're working on two projects to communicate with Micron Flash Memory. The first one called the SPI project, uses the SPI 4-wire IP core and SPI driver. In the second project, known as the GSFI project, we're using the Generic Serial Flash Interface IP Core with the GSFI HAL driver. The protocol used in the GSFI project is Standard SPI.
In the SPI project, when we use the alt_avalon_spi_command() function to write a page of Flash memory, everything goes smoothly. The Chip-Select signal goes low, then we send the Page Program command, address, and data. Each byte of data is sent to the flash memory one at a time.
But in the GSFI project, when we use the intel_gsfi_write_block() function to write a page in the Flash memory, things are a bit different. For every 4-byte data segment, the GSFI core first sends a Write Enable command. Then it sends the Page Program command, address, and the 4-byte data. After that, it checks the Status Register. This process repeats for each 4-byte segment, creating a lot of overhead.
We're looking for help in understanding why the GSFI core behaves differently compared to the simpler SPI method used in the SPI project. In fact, we are wondering why GSFI IP Core sends the Page Program command and address for each 4-byte data, instead of sending data as a burst, as explained above.
Note: We're using Intel Quartus Prime Pro Edition on Agilex 7 SoC.
