Cyclone V PCIe End Point Configuration Space register default values

I think the purpose of tl_cfg_ctl is to collect some important PCIe registers thus user can check them at one place. The arrangement of these registers could be somewhat confused since the offset now is not the offset in PCIe spec.

Please notice that both tl_cfg_tl_cfg_ctl and tl_cfg_tl_cfg_add are output signals. The doc says "They update every eight coreclkout_hip cycles" that means these two signals continue sending out data. Therefore you can have registers collecting them for you to check.

For example, when tl_cfg_tl_cfg_ctl=0x0040_0002 and tl_cfg_tl_cfg_add =0x2, the cfg_link_ctrl2[15:0]=0x0002 in link control 2 register means target link speed is gen2.

Regards,

Rong