Cyclone V PCIe End Point Configuration Space register default values

Hi

the goal of this effort is to figure out the actual default starting values prior to system negotiation for PCIe link training that is the value of what is programmed into the register by default from the FPGA IP Core, the Cyclone V Avalon Memory Mapped Interface for PCI Express Solutions User Guide (table 4-12) is very confusing on the matter if not conflicting with the PCI SIG definition of the register. hence i am trying to figure out if the user guide has a typo and the FPGA code has the correct value or are both set differently?