Occasional ContributorAgilex5: How to use a GTS refclk to clock the FPGA fabric?
I tried to use the GTS System PLL configured with FABRIC_USE_CASE and ref clock frequency to 156.25MHz, C1 enable and selected 101.768092 MHz from the C1 output frequency menu but this results in the following error:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 I/O pad(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.intel.com/content/www/us/en/support/programmable/kdb-filter.html and search for this specific error message number.
Error (175019): Illegal constraint of I/O pad to the location PIN_AT120
Info (14596): Information about the failing component(s):
Info (175028): The I/O pad name(s): pad_spf_refclk_p
Error (16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error (175006): There is no routing connectivity between the I/O pad and destination I/O input buffer
Info (175027): Destination: I/O input buffer pad_spf_refclk_p~input
Error (175022): The I/O pad could not be placed in any location to satisfy its connectivity requirements
Error (175022): The destination I/O input buffer could not be placed in any location to satisfy its connectivity requirements
Info (175029): 1 location affected
Info (175029): PIN_AT120PIN_AT120 is REFCLK_GTSL1C_RX_P on the Arrow AXE5-Eagle board.
I also tried to use the regular IOPLL but it results in the same error.
How can I use the GTS refclk to clock the FPGA fabric?
Hi,
posted minimal design doesn't work because it doesn't connect system PLL output to anything, thus the PLL is discarded during synthesis.
Modified top.sv respectivelyassign {//pad_rled0, pad_gled0, pad_bled0, pad_rled1, pad_gled1, pad_bled1, pad_rled2, pad_gled2, pad_bled2, pad_rled3, pad_gled3, pad_bled3} = 11'o213; //12'o4213; assign pad_dbg_tx = pad_dbg_rx; assign pad_rled0 = clk101p768092; assign clk101p768092_ready = 1'b1;
Connecting the PLL reveals another error. The fact that you never got to this point suggests that the PLL wasn't implemented in your design, e.g. due to missing connectivity.Error(22849): Intel FPGA IP instantiated in the design requires the DEVICE_INITIALIZATION_CLOCK option to be set to either OSC_CLK_1_25MHZ, OSC_CLK_1_100MHZ, or OSC_CLK_1_125MHZ. This assignment is missing in the QSF file.
Added
set_global_assignment -name DEVICE_INITIALIZATION_CLOCK OSC_CLK_1_100MHZ
Get still complains about missing constraints, but design basically compiles now.
Regards
Frank
P.S.: Don't know, if DEVICE_INITIALIZATION_CLOCK is actually required to run system_pll. GTS PHY itself needs it according to device handbook.
