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wangduoyu's avatar
wangduoyu
Icon for New Contributor rankNew Contributor
8 months ago

Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP

Hi all,

I'm developing on the Agilex 5 platform and need two AXI4 masters to access the DDR.

I noticed there isn't a standalone IP similar to Xilinx's axi_interconnect. Is it correct to simply connect two AXI masters directly to the single DDR AXI slave port (as shown below)? Will the interconnect fabric generate the necessary arbitration and routing logic in this case？

 

general
Memory
Other Ips

4 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    8 months ago

    Hello,

     

    The Platform Designer will handle the arbitration logic for this type of connection.

    I think you can check that in the Interconnect window/view.

     

    Regards,

    Adzim

    • wangduoyu's avatar
      wangduoyu
      Icon for New Contributor rankNew Contributor
      8 months ago

      Thanks. Is it necessary to use an AXI Bridge to solve the addressing issue?

      • AdzimZM_Altera's avatar
        AdzimZM_Altera
        Icon for Regular Contributor rankRegular Contributor
        8 months ago

        Hello wangduoyu,

        I'm glad that your issue is resolved. I will continue to monitor this post for the next 5 days. If there are no further inquiries during this period, I will step back and allow the community to assist with any future follow-up questions.

        Thank you for engaging with us!

        Regards,

        Adzim