access the registers of the JESD204B IP

Hi David

Users can dynamically change the configuration of the JESD204B IP core base and PHY layers through TCL scripts (System Console control) or through embedded C programming (Nios subsystem control).

Kindly refer to 'JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide"

HTML: https://cdrdv2.intel.com/v1/dl/getContent/683113

PDF: https://www.intel.com/content/www/us/en/docs/programmable/683113/

The structure of the design example varies depending on the values of these JESD204B IP core parameters:

• Data path:

Duplex: Both TX and RX data paths and CSR interfaces present

TX only: Only TX data path and CSR interface present

RX only: Only RX data path and CSR interface present

• Transceiver dynamic reconfiguration mode:

- When enabled, transceiver PHY reconfiguration interface is present in the design example and connected the JTAG to Avalon master bridge (System Console control) or Nios subsystem (Nios control) module.

- When disabled, transceiver PHY reconfiguration interface not present in design example.

The generated design example is a self-contained system with its own JESD204B IP

core instantiation that is separate from the IP core that is generated from the IP tab.

The JESD204B IP base core and PHY layer connect to System Console or Nios

subsystem through the Avalon memory-mapped interconnect. The JESD204B IP core

uses three separate Avalon memory-mapped ports:

• Base core TX data path— For dynamic reconfiguration of the TX CSR parameters

• Base core RX data path— For dynamic reconfiguration of the RX CSR parameters

• PHY layer— For dynamic reconfiguration of transceiver PHY CSR