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Altera_Forum's avatar
Altera_Forum
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15 years ago

VHDL Numeric Type Conversion

I am using a bunch of variables to do some math. These variables, X and Y coordinates, are converted to different numeric types for ease of math operations. The outputs, Xm and Ym, are SLV's and depe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

There is nothing here to show a problem. Are you sure the problem isnt elsewhere?

Out of interest, why do you do so many conversions? If this is not the top level, why not just leave all the ports as integers?

Also. If you want to divide by 2, do a divide by 2. The synthesisor will recognise it as a right shift:

Yx_sv <= Yx_sc1/2;