VHDL - CASE related question

You are right.

I began writing with other types (you had said) for port. And I finally adopt this method.

This is less obscure, simpler to "debug"....

Thanks

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port type in entities :

only std_logic(_vector) : Yes, conversions are annoying but more re-usable. I think about "design re-use".

I will study that question : I have wanted to keep a certain rigor in VHDL designing. Thanks for your opinion.

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With Quartus (and other tools) supporting other things other than std_logic there is no reason to write what you mean. Doing all the type conversions just kills the whole point of types in VHDL, which are there for code readability. Adding in coversions all over the place makes the code more obscure.

I should add that

you will learn by (good) VHDL examples and tutorials on the web (Altera and others).

They represent many "basic" VHDL codes that you can understand very well.

port type in entities :

only std_logic(_vector) : Yes, conversions are annoying but more re-usable. I think about "design re-use".

I will study that question : I have wanted to keep a certain rigor in VHDL designing. Thanks for your opinion.

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an FPGA has no instructions, only logic gates and registers, so thats not a correct question to ask. You could write a CPU using VHDL and then you could ask your question about your CPU, not the FPGA.

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Thank you Tricky!

I get that now. When you compile it will create whatever we want in digital logic. So as long as there are enough of those parts I can do any amount of assignments inside. Thank you very much.

Yes I do have a long way to go before I really start coding. Thank you for the help Tricky.

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Thank you very mcuh Tricky, mmTsuchi.

Looks like a have long way to go.

One thing that I can't understand is,

A GENERATE block and a PROCESS block, 'how many' instructions can a FPGA perform? It ofcourse depends on the model, but as a programmer, how would you know that a block of code can be executed within a clock cycle? Or is it not like that? Is possible for a block of PROCESS to take several clock cycles to execute completely?

Thank you.

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an FPGA has no instructions, only logic gates and registers, so thats not a correct question to ask. You could write a CPU using VHDL and then you could ask your question about your CPU, not the FPGA.

A clocked Process will ALWAYS complete all code lines in a single clock cycle (assuming the FPGA can meet timing requirements), but thats may not be what you understand.

for example:

signal a, b : std_logic;
process(clk)
begin
  if rising_edge(clk) then
    a <= input
    b <= a;
    output <= b;
  end if;
end process;

The code inside the process executes on every single clock cycle. The process discribed 3 registers connected. So it would take 3 clock cycles to get the input to the output. This is a 3 stage register pipeline.

The output would produce a new value every single clock cycle, delayed by 3 clocks.

I could put a generate block around this process like this:

multi_pipeline_gen : for i in 0 to 3 generate
  --put process from before here
end generate multi_pipeline_gen;

and you get 4 parallel pipelines. Basically a process describes one bit of hardware, a generate tells you to replicated that hardware n times.

It sounds like you dont have a great understanding of digital electronics. Forget about VHDL for now and go and read up about digital logic.

Thank you very mcuh Tricky, mmTsuchi.

Looks like a have long way to go.

One thing that I can't understand is,

A GENERATE block and a PROCESS block, 'how many' instructions can a FPGA perform? It ofcourse depends on the model, but as a programmer, how would you know that a block of code can be executed within a clock cycle? Or is it not like that? Is possible for a block of PROCESS to take several clock cycles to execute completely?

Thank you.

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I recommend to use only std_(u)logic, std_(u)ogic_vector(... downto ...) for ports of an entity.

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Personally, Id recommend having ports on entities of the type that best reflects what it is. Its so annoying have to do type conversions all the time when 2 connected entites are using integers and signed/unsigned types internally. At the top level you will need to use std_logic(_vector) or signed/unsigned though because you have to constrain individual bits to single pins. But internally, use whatever best reflects what the signal actually is.

Types Ive used fine for ports on entities (not top level)

Std_(u)logic(_vector)

signed

unsigned

boolean

integer/natural/positve (remember to constrain them else you'll have lots of spare bits)

sfixed/ufixed

records containing any of the above

arrays of any of the above

Records come into play when you're trying to encapsulate stuff, especially registers.

also, ennumerated types should be fine as port connections.

In addition, memories can be infered from most of the above.

Completely agree with Tricky.

Altera gives on website guidelines and coding style like http://www.altera.com/literature/hb/qts/qts_qii51007.pdf?gsa_pos=3&wt.oss_r=1&wt.oss=vhdl%20guidelines

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LIBRARY ieee;

USE ieee.STD_LOGIC_1164.all;

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I recommend to use only std_(u)logic, std_(u)ogic_vector(... downto ...) for ports of an entity.

Be aware of what is synthesizable or not (like "after 25 ns", file operations...)

...

think about circuit and describe it in vhdl.

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About that VHDL is a not a programming language, I can understand that it is different from C++/Java/etc., in the sense that it is concurrent, synchronous, etc., but is there something important you need to keep in mind when writing VHDL? For someone new to VHDL and coming from a C++/Java background.

Thank you.

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before even typing 1 letter of VHDL, first think about the circuit you want to create. As VHDL is a description language, not a programming language, you are only ever describing a circuit you already know.

What confuses people is that you can do alot in VHDL that is very C++ like, but actually wont do anything for you when you compile it - alot of this functionality is there only for testing and modelling purposes (for example, I have functions that can read/write bitmap files) but is in no way synthesizable.

If you keep to the first rule - you'll improve your VHDL massivly.