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dncmrc1's avatar
dncmrc1
Icon for Occasional Contributor rankOccasional Contributor
11 days ago

Stratix 10 fPLL pre-calibration

We need to switch (reconfigure) the Stratix 10 fPLL clock rate without waiting for its automatic calibration.

For the Arria 10 we disable the automatic calibration and, after power-up, we command a "manual" pre-calibration, read the calibration results from fPLL registers and store the calibration results in our temporary registers. We do that for a number of clock rates and create a table of calibration results.

Then, when clock rate needs to be changed, we just rewrite the calibration results from our temporary registers back to the fPLL registers, choosing the correct clock rate. This is much faster and works very well.

For the Stratix 10 we would like to know what are the addresses and the bit masks of the calibration result registers we need to store and to rewrite.

Core Logic

2 Replies

  • dncmrc1's avatar
    dncmrc1
    Icon for Occasional Contributor rankOccasional Contributor
    4 days ago

    We need to know about those not publicly documented PLL registers. Please let me know in a private message who should we contact to know about them e.g. signing an NDA. Thanks!

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 days ago

    The specific register addresses and bit masks for Stratix 10 fPLL calibration results are not publicly documented in the user guides. This represents the differences in the PLL Architecture from Arria 10.

     

    The available Register Information that I found in Arria 10 is the fPLL Calibration Enable Registers, where the Offset Address is 0x100.