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JohnHaraguchi's avatar
JohnHaraguchi
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1 month ago

Stratix 10 CKEXT Drive Level 32 GHz Clock

Hello,

The S10 datasheet lists the CKEXT differential input power requirement as +1.9 to +7.9 dBm at 32 GHz.

Is the lower limit required to meet all performance parameters or a hard limit where the S10 will not function if not met?

If the differential clock power is 0 dBm, does the S10 operate with degraded performance or stop working altogether.

On our assembly CKEXT will be borderline to meeting the minimum +1.9 dBm input level.

I'm planning to test the input power after we receive our assemblies, but was looking for guidance on what to expect.

Thanks,
John

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1 Reply

  • JonWay_altera's avatar
    JonWay_altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    The +1.9 dBm lower CKEXT requirement should be viewed as a performance‑validated limit rather than a hard functional cutoff: if the CKEXT drive drops below +1.9 dBm, the Stratix 10 will generally continue to operate, but you may encounter reduced jitter margin, higher BER, or less‑stable PLL locking, and while a drive level around 0 dBm usually won’t prevent the clock path or PLL from functioning outright, it does fall outside Intel’s guaranteed operating conditions, meaning that signal integrity degrades and published timing and jitter specifications may no longer be met—so it’s best to treat +1.9 dBm as the minimum level needed for full, spec‑compliant transceiver and PLL performance.