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Altera_Forum
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9 years ago

Soft-Serdes for LVDS Issues

Hello Everyone, We are using EP4SGX230KF40I3 deivces in our project. Each FPGA will process 6 LTM9010 (8-channels ADC). The ADC's sampling rate is 100M. LTM9010's output speed is limitted no mo...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Did you try ALTLVDS megafunction? I think it will automatically generate all necessary logic.