Self clocking FPGA?

Thanks Dave - but this design is in production and we are not going to change the PCB for this "feature".

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The configuration clock isn't always disabled after configuration, you can use it through the ALTINT_OSC megafunction (in the I/O category). It's not documented though, AFAIK.

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Now this looks promising!

Here is the code that pops out of the wizard:

module  internal_clk_altint_osc_947
	( 
	clkout,
	oscena) ;
	output   clkout;
	input   oscena;
	wire  wire_cycloneiii_oscillator1_clkout;
	cycloneiii_oscillator   cycloneiii_oscillator1
	( 
	.clkout(wire_cycloneiii_oscillator1_clkout),
	.oscena(oscena));
	assign
		clkout = wire_cycloneiii_oscillator1_clkout;
endmodule //internal_clk_altint_osc_947

It looks like the input is an enable - the only question is the level, but I'm going to guess logic high... I'll post my experimental results as I try it.