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corestar's avatar
corestar
Icon for Contributor rankContributor
3 years ago
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Using multiple LVDS ADC in a single Arria 10 GX IO bank

I want to use 8 LTC2271 16-bit ADC in an Arria 10 GX 320. They use serial LVDS and each one needs 4 LVDS pairs (bit clock, frame clock and 2 data lanes). The FPGA has 8 IO banks, so we could clearly ...
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  • FvM's avatar
    FvM
    3 years ago

    Hi,
    it's not generally necessary to connect DCO and FRAME clock of all ADCs. There are different choices to acquire the serial data.

    - use individual DCO and FRAME clock but no RX PLL. At least DCO must use dedicated clock input.

    - use FRAME clock and PLL per ADC, generate bit clock internally. FRAME must use dedicated clock input
    - if delay skew between individual ADC is small enough (e.g. no additional buffers and long traces involved), use common DCO and FRAME clock for all ADC
    - if you are unsure about delay skew but want to avoid individual clock inputs for each ADC, you can use soft CDR with training pattern on startup. Need to connect ADC SPI interface

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi,
sorry for delay.

- yes, you don't need necessarily RX PLL. Might need to setup your own deserializer because SERDES IP probably doesn't support this operation mode, but I didn't try on newer devices with SERDES IP. Major drawback is requirement of a dedicated clock input per ADC. Just wanted to mention the option.

- I agree that DPA solution is probably overengineering for rather slow 320 MSPS.

- You don't tell how you want to set clock phase with your (single) external PLL solution. If phase isn't measured and adjusted online (DPA/soft-CDR solution), it has to be preset to a fixed value. How is this different from my suggestion to use common DCO and frame clock? You can at best compensate for known trace delay differences by setting individual phase shift.

corestar's avatar
corestar
Icon for Contributor rankContributor
3 years ago

@FvM,

- yes, you don't need necessarily RX PLL. Might need to setup your own deserializer because SERDES IP probably doesn't support this operation mode, but I didn't try on newer devices with SERDES IP. Major drawback is requirement of a dedicated clock input per ADC. Just wanted to mention the option.

I think I understand. A shame to waste the SERDES though. Also, the LTC2271 was an example. We may go to higher speed.

- You don't tell how you want to set clock phase with your (single) external PLL solution. If phase isn't measured and adjusted online (DPA/soft-CDR solution), it has to be preset to a fixed value. How is this different from my suggestion to use common DCO and frame clock? You can at best compensate for known trace delay differences by setting individual phase shift.

If you're referring to my question of if I could use an fPLL, I meant to say I would use an fPLL per ADC, not one for all of them. Some banks have multiple clock inputs which would determine how many ADC per bank. Of course, would have to try it and see if the tools complain.

But a better way might be your last suggestion. Say I want four ADC on a bank:

  1. Create 4 ALT_LVDS cores in external PLL mode with DPA.
  2. Feed the DCO from one ADC into the IOPLL on that bank
  3. Use DPA on all LVDS data lines.
  4. Use test pattern to do bit-slip per ADC

It seem to me, the DPA would be off by at most half of 45 degrees or 22.5 degrees. In practice, the perfectly centered 90 degree offset option of the LTC2271 will have some variation anyway.

This would actually save alot of traces. No need for FRAME clocks at all (true of any solution) and really only need the DCO from say a fourth of the ADC.

Of course, you never know what the tools will complain about. It's all a bit unclear still.

Thanks for the help.