Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorRandom single hold violations on Arria V design that doesn't push timing or util. ???
Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- there are no analogue buffers in FPGAs. --- Quote End --- so how does Quartus fix timing violations caused by clock skew? (sorry, I'm an ASIC guy where adding delay buffers is how you fix hold vios). --- Quote Start --- LUT based multipliers will have poorer timing performance that the hard ones.. --- Quote End --- you think? :-) /j
