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Altera_Forum
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11 years ago

Random single hold violations on Arria V design that doesn't push timing or util. ???

Hi - I have a design that uses about 20% of the FPGA Fabric on an ArriaVSoc. I've added my own logic to the GHRD. It doesn't push timing (my logic is 100MHz or less), or utilization (see above, eve...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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there are no analogue buffers in FPGAs.

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so how does Quartus fix timing violations caused by clock skew? (sorry, I'm an ASIC guy where adding delay buffers is how you fix hold vios).

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LUT based multipliers will have poorer timing performance that the hard ones..

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you think? :-)

/j