PLL locking and reset generation in Cyclone III

Many thanks or your help kaz!

Although your answer is a bit concise (for a beginner) I hope I decrypted in your message a few important points about reset related issues.

I'll try to explain (in a verbose style) what I understood. I'll thank you in advance for your additional comment.

First, I understand that the FPGA ALWAYS starts with all FF reset (at 0) after configuration is finished. I also understood that users can define the initial values in the HDL code. (However, defining an initial value of 1 for a FF will be implemented by the NOT gate push-back because all FF start at 0.)

In addition, users can apply an explicit reset signal to the asynchronous clear port of FFs. This explicit reset is needed, for instance, if the clock signal is not guaranteed to be stabilized at the end of device configuration. This reset should be applied at power-up and maintained until system clock is guaranteed to be stabilized. A way for detecting clock stabilization is to monitor the "locked" output from the PLL.

Then, comes the issue of releasing the asynchronous reset signal that you point out. Therefore, when you say "<...> using some initial logic that is protected from release problems e.g. counter starting at 0 until 3 then stop and release the reset.", I ask, how do you release the reset the "0-to-3 counter" itself?

May the "0-to-3 counter" have an asynchronous reset? Would it be acceptable practice to use combinational logic using the PLL "locked" output to drive the asynchronous clear of the "0-to-3 counter"? Thus, if my understanding is correct, this counter would be the single component in the system having an asynchronous (thus, to some extent, unreliable and unsafe) reset, whilst all remaining FF in the system would have their clear input driven by the synchronized (thus, safe) counter output. Right?

I might have used a lot of wording to reformulate the same thing in your message. I'll be happy if you could confirm my understanding and drop some more comment if I got it wrong!

Thank you again