OpenCore Designs Validate—Stratix III FPGA Advantages Increase with Design Size

Question

Hi all, I recently found this interesting article about the comparison of Stratix-3 vs Virtex-5 at http://www.altera.com/products/devices/stratix-fpgas/stratix-iii/overview/architecture/performance/st3-opencores.html#benchmarking_and_stamping_methodology

I was trying to figure out what they mean about "compile time" (e.g. if they include par) but I couldn't. I wanted to compare the results using another device (different vendor) and I need to know if par has to be included in the evaluation (it is the critical part in my tool).

Thanks,

Luciano

altera_forum · Answer

Compile times includes Synthesis, Place and Route.

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OpenCore Designs Validate—Stratix III FPGA Advantages Increase with Design Size

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