Making a counter from 50MHz Clock?

Sorry,

Work and school got a bit overwhelming...

I'm able to spend a few days working on some VHDL now :)

I will try to comment your code to confirm i understand it.

--- Quote Start ---

process(clk)
variable count : unsigned(26 downto 0) := (others => '0');  //why others => '0'?
begin
if rising_edge(clk) then
    if count > 50000000-1 then
         count := count - 50000000;    //set count to 0
    else
         count := count + 3579545;     //very clever "modulo" does it really work as such?
    end if;
    my_clk <= std_logic(count(25));  //passes bit 25 and uses as a clock signal
end if;
end process;

--- Quote End ---

thanks for your help!!