Contributor
Contributor
The data was taken by the logic analyzer with a resolution of 2 ns. The logic analyzer threshold was set to 1.65V.
1. Oscillogram with 3 cycles (attempts) of the configuration. You can see how many (approximately) bytes of data were received when reading in the corresponding CS window. The place where the configuration process was terminated is marked green with the FINAL_DATA signature.
2. Here, you can see the moments of the request STATUS_REGISTER (0x05), DEVICE_ID (0x9F) and FAST_READ (0x0B) with addresses 0x000000 and 0x00012C.
3. In these images, you can see in detail the requests STATUS_REGISTER (0x05) and DEVICE_ID (0x9F).
5. The start of the FAST_READ(0x0B) operation from the address 0x000000 is shown. There is a strange pause in the clock signal in SCLK (marked in green).
6.The moment of configuration process termination (the FINAL_DATA area from the first image). Why might the configuration get interrupted?
ContributorI also want to add some valuable information.
In the previous version of the project, I used the same connection scheme with Micron memory.
Everything worked.
We can, if necessary, try installing Micron flash on the current board for testing.
