LVDS TX/RX Pin Assignment Error in Quartus – Unable to Resolve

Hi Team,

I am facing a pin assignment issue with LVDS TX and RX IP in Quartus Prime.

I have tried all the suggestions provided earlier (bank selection, I/O standard, refclk, PLL connections, and pin constraints),

but I am still encountering pin assignment errors during compilation.

Details:

- Device: AGIB022R31A2I2VB

- Tool: Quartus Prime 25.1.1

- LVDS IP: TX and RX

- Mode: External pll mode in both TX and RX

- Issue: Pin assignment errors related to LVDS TX/RX signals

I have verified:

- Correct I/O banks and VCCIO

- Differential pair placement

- Dedicated reference clock usage

- PLL lock status

Despite this, the issue persists.

I have attached all relevant files:

- .qsf

If possible, could someone please:

1. Review the attached files and point out what might be wrong, OR

2. Share a small working reference project for LVDS TX/RX pin assignment

I am also open to discussing this over a call if needed, as it may be easier to debug.

Any guidance would be appreciated.

Thanks & Regards,

Hari