Loading EPCS with Nios without JTAG

Hello out there,

I have had an ongoing SR with Altera for two weeks now and I don't think they understand my situation.

Frustration with Altera is growing by the hour. :angry:

I have a custom board and just trying to get the most basic nios to run:

After this loading our complete project should not be much different. (hopefully) :unsure:

Using EPCS16

Cyclone III (EP3C25F256C8N)

Single-Device AS mode, MSEL[0..2]="010"

JTAG is DISABLED, Altera keeps missing this part and refering to the flash programmer which doesn't find a target JTAG

Using the 9.0 software. And even tried the 9.0sp1 and 8.1 we have backups of the old versions.

I can program a Quartus II hardware image to the EPCS16 fine.

(I convert the sof to a pof and download over USB-Blaster using Quartus II programmer in AS mode)

(I need to disconnect the USB-Blaster cable and cycle the power one time and it runs fine)

(Not sure if that should be needed and might be a source of an issue.)

I have in SOPC:

cpu_0 (reset vector-epcs_flash_controller_0 Offset 0x0 / No debugger since no JTAG /

epcs_flash_controller_ controller_0 (IRQ 0)

nios_ram 32k

test_pin pio for output tests

sysid sysid check

In Nios:

A simple counter that outputs to the test pins.

How can I create a similar SINGLE download that includes a Quartus II hardware and Nios II including bootloader and code in the proper places?

I am getting more confused with which parts Altera auto assembles and which things they do not.

They have me doing the sof2flash, elf2flash, and nios2-elf-objcopy srec to hex and then combining parts of them.

to get a pof + hex data but this isn't working.

When I did the elf2flash conversion I had to change directories and copy the sof/flash from the quartus directory over to get it to work which tells me that the two projects are not fully seeing each other.

I am not sure if the hex addresses are correct or if the bootloader is even getting loaded.

What triggers the Nios II bootloader?

Is the bootloader part of the hardware image that sets the initial on-chip ram?

Where in memory is the bootloader stored so I could check some of the addresses in the hex files?

What triggers the bootloader to begin copying?

What triggers the copied source code to begin running?

Thank you so much for any help on this.