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Altera_Forum
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14 years ago

is VHDL unsafe with state machine?

Typical VHDL state machine is to define a type that consist of states, then use that type in a signal. But if someone (not me, no way! ;-)) forget to put a reset state, the state machine continues to...
Altera_Forum's avatar
Altera_Forum
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14 years ago

As FvM points out, the VHDL language is essentially changing your code to:

signal currState, nextState : state_type := S0;

Which is a synthesizeable construct; whatever Quartus decides is the state width, and the encoding for S0, the registers will be initialized to at power-on.

If STARTUPSTATE should be first, then either the enumeration can be changed, or the code changed to

signal currState, nextState : state_type := STARTUPSTATE;

or, explicitly use a reset signal and initialize the state in the process as you have shown. However, even in that case, if you never assert reset in the simulation, the state variables will be assigned to either S0 or whatever you explicitly assign to.

Personally I prefer the explicit use of a reset signal.

Cheers,

Dave