IQ down converting speed

If your ADC is taking 6 cycles to read at 300MHz clock rate, then your ADC interface sounds a bit strange.

I interface 1GHz dual-channel ADCs into Stratix II devices. The digitizers output 1Gbps signals which can be captured using the LVDS on the Stratix II. On a Stratix III you should be able to do something similar. I'm not sure what the LVDS limit on Cyclone III is.

However, it sounds like you are only wanting to sample a signal centered on 10MHz, and if you can really only read every 6th sample from your ADC operating at 300MHz, then your effective sampling frequency is only 300MHz/6 = 50MHz, so 25MHz is your Nyquist frequency.

Your external signal will need an analog filter that causes the signal amplitude to start to fall off at 10MHz (or whereever your signal is located) and by the time you get to 25MHz+15MHz = 40MHz, the signal power needs to be below your desired signal power at 10MHz (the signal at 40MHz will alias onto your signal at 10MHz when you sample at 25MHz).

Once the signal is sampled, and is inside the FPGA, you have to make sure you preserve the SNR you desire your signal to have though your digital processing, eg., you need to make sure you carry the right number of bits in your NCO and the output of your NCO.

The decimation rate you are considering 10MHz/100kHz is about 100x so you should be able to decimate using a multi-state design consisting of a CIC filter, followed by a pass-band cleanup filter (FIR or half-band). If you do not know these DSP terms, browse around MATLABs web. If you have a MATLAB license, you can use FDATool and the Filter Designer Toolbox to figure out what kind of filtering you need, then work your way through to an FPGA implementation.

If you don't have the tool then provide a clearer explanation of your design, and perhaps someone will provide an example design for you. For example, is the signal you are trying to demodulate at a fixed location? Can you change the ADC interface so that it can be run at 300MHz, if so, then your external filtering becomes simple, and you have more flexibility in your DSP code.

Cheers,

Dave

FPGA based digital signal processing generally uses pipelined datapathes, latency times don't affect the throughput. This is also the case with pipelined high speed ADC.

You can generally assume, that FPGA based DSP can handle data streams up to the ADC sampling rate, if the required interface is supported by the respective FPGA family. The faster core and periperals of Stratix family eases the design of DSP at speeds of 100 MHz and above. In so far, design economy may suggests to choose high performance FPGA. But 100 MHz sampling rate can be handled by Cyclone designs as well.

If 300MHz processing means 6 channels x 50MHz each then you can process as many as suits your final speed. You don't have to process all in parallel or all in serial.

It is a case of resource-speed trade-off.

For stratix II I believe 200MHz is the comfortable limit. for stratix IV it could be 350MHz. So stratix III may in between.

For very fast sections at io you can use ddio or serdes as a speed bridge

I am not sure about cyclone speed.

thanks all for the input

I am testing using a Straix III dev board with a parrallel single ended adc (65MHz) that i used on another project (only sampling at 4MHz into a cyclone III). My ADC VHDL state machine needed 6 clocks as it includes the ast signals SOP, EOP, Valid (originally 2 channel I & Q).

My choice of 10.7MHz IF is simply becuase it is a traditional IF and the RF filtering components are readily available.

konrad

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My ADC VHDL state machine needed 6 clocks as it includes the ast signals SOP, EOP, Valid.

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Doesn't sound to be a reasonable way for 65 MHz sampling speed ...

I can read the ADC quickly but how else do you generate the AST output required for the FIR filter (I am using the mega-function)?

I could easily change the adc but I still need to generate the Avalon signals.

Am I taking the wrong approach?

Konrad