New ContributorHow to set initial register values after powerup
Hello,
A topic that has been written about a few times. But how to make sure a specific register value is set, after the FPGA has powered up?
I have learned that setting an initial value have no effect other than in simulation.
I have a specific case where I want a specific value to by 10. So far I have made it so, that I use an external reset signal/pin to force all my registers into their "start" state.
But is there a more clever way that this can be done in VHDL instead. I use Cyclone IV and have read that some Altera devices have this "Reset Release" IP avilable that do a reset after powerup.
Thank you.
Hi,
internal register POR state is generally inferred from initialization statements. While std_logic entities have a default initial value of 'U' in simulation, the default initial value of synthesized signals and variables is '0'. It can be overridden by an explicite initial value in declaration.
Besides initial value, POR can be also set by a reset statement. If reset value is different from initial value you get a synthesis warning that initial value is ignored.
Regards Frank
P.S.
Automatic POR and external reset signal don't necessarily cause consistent design state because they are asynchronous to design clock. They can cause unexpected initial counter or even illegal FSM states. Synchronous reset release avoids this problem and should be coded in HDL if no respective IP is available. It must be used with explicite reset statement for respective signals.
