How to reduce the area of my design?

Question

Hi all,

I'm doing an FPGA design with Stratix 3; And our design doesn't fit into a single chip. Our FPGA has 38000 Combinational ALUTs and 38000 dedicated logic registers;

Our design takes about 39000+ Combinational ALUTs(105%) and 43000 registers(115%). But I noticed that it only takes very few Memory ALUTs. Is it possible that my design could be implemented usiing Memory ALUTs?

And what should I do to squeeze our design a little bit such that it could fit in a single chip? I have tried to manipulate some settings in quartus and it doesn't seem to work. Is there any way to optimize my verilog code in terms of area?

Thanks in advance:)

altera_forum · Answer

And another question here:

the report shows that the logic utilization is 55100/38000 （145%）

How is it possible to reach 30% if my Combinational ALUTs utilization is 105% and my dedicated registers' is only 115%?

altera_forum · Answer

--- Quote Start ---

And another question here:

the report shows that the logic utilization is 55100/38000 （145%）

How is it possible to reach 30% if my Combinational ALUTs utilization is 105% and my dedicated registers' is only 115%?

--- Quote End ---

Hi,

are you using shift registers and fifos in your design ?

Kind regards

GPK

altera_forum · Answer

I would go through the fit report and see which entities are using the most logic - and then see if you could afford to change their size.

altera_forum · Answer

if your design is so much exceed your FPGA, i don't think that different compilation guidelines would solve the problem.

I think that you should think creatively about logical reduction, i.e. if you have few instances of the same module, maybe you can create single module which operates in time sharing? or use the FPGA memory as ROM tables instead of complex logic?

altera_forum · Answer

Post your question only once please. Duplicate threads are deleted.

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How to reduce the area of my design?

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