Forum Discussion
Altera_Forum
Honored Contributor
12 years ago --- Quote Start --- The simulator does not know about chips, it just knows about HDL code, so your simulation of two FPGAs is a top-level design containing two instances of a transceiver block with TX1->RX2 and RX1->TX2. You could also think of this as one chip with two transceiver blocks connected. Cheers, Dave --- Quote End --- Ok, i think i understand you!