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Altera_Forum
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17 years ago

Frequency Counter in Verilog?

Hi all, im trying to measure a squarewave frequency which is coming from a tacho. The first implementation i tried used a known frequency and between rising edges of this frequency the rising e...
Altera_Forum's avatar
Altera_Forum
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11 years ago

--- Quote Start --- 


// Resynchronize in_clock to ref_clock domain
always @(posedge ref_clock)
                    in_clock_rsync  <= {in_clock_rsync,in_clock};
endmodule

Jake

--- Quote End ---

the 3-bit wide in_clock_rsync is never used..

did you mean 


always @(posedge in_clock_rsync   or negedge reset_n)
    if(!reset_n) 
    begin
        count           <= 32'd0;           // reset counter
        f_measurment    <= 32'd0;           // reset output
    end 
...