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Altera_Forum's avatar
Altera_Forum
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11 years ago

FIR Compiler II TDM Problems

Hello

I' working for the first time on a simple single rate FIR filter implementation with a 13 Bit input data stream. The filter works fine when I use the same frequency for the FIR clock and the sample rate.

I connected the following:

clk: sample rate (1.82 MHz)

reset_n: VCC

coeff_in_clk: sample rate (1.82 MHz)

coeff_in_areset: VCC

ast_sink_data[12..0]: 13 Bit width input data stream

ast_sink_valid: VCC

ast_sink_error[1..0]: not connected

Because the sample rate is only 1.82MHz I want to clock the filter with 116.48MHz system clock (TDM Factor of 64) to save resources. In the compilation report I can see that the FIR Compiler has

optimized the filter because of the higher clock. Know it needs much less multipliers as before.

I connected the following for the TDM test:

clk: system clock (116.48 MHz)

reset_n: VCC

coeff_in_clk: system clock (116.48 MHz)

coeff_in_areset: VCC

ast_sink_data[12..0]: 13 Bit width input data stream

ast_sink_valid: VCC

ast_sink_error[1..0]: not connected

When I check the output of the filter it does not work right. There are different higher frequency components in the signal that should be cutted by the filter.

Is there something to observe with the valid input when you work with a tdm factor? I can't find something about this in the manual.

Is this a known problem or can anyone give me some hints to solve it?

Thanks for your answers and best regards

Ueli Giger

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    If I understood you. You have one channel data but tdm factor 64 and input clk is 116.48MHz, data rate is /164 of that so you need to make valid in 1 in 64 as well to indicate which data slots are valid.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes I have one channel with a data rate of 1.82MHz and the clock of the FIR filter is 116.48 MHz -> tdm factor of 64. I set the data valid input continous to high. But with thos settings the filter does not work correctly.

    Sorry but I did not understand your whole answer. Is it right to put the valid input to 1 all the time? Or what do you mean with "make valid in 1 in 64 as well to indicate which data slots are valid"
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Yes I have one channel with a data rate of 1.82MHz and the clock of the FIR filter is 116.48 MHz -> tdm factor of 64. I set the data valid input continous to high. But with thos settings the filter does not work correctly.

    Sorry but I did not understand your whole answer. Is it right to put the valid input to 1 all the time? Or what do you mean with "make valid in 1 in 64 as well to indicate which data slots are valid"

    --- Quote End ---

    setting valid to 1 all the time means the filter will see each sample repeated 64 times and so is wrong. valid must 1 for one clock then low for 63 clocks and repeat that pattern.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    I tried it out and now the filter works perfectly.

    Many thanks for your help!!!