Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

DE2_top not compiling

In trying to teach myself Verilog. I am having trouble compiling the most basic of functions

I just have the DE2_top file which is nothing more than a list of all the pins and an endmodule command written at the bottom in a folder labeled "test" upon compiling it keeps telling me that "test" is undefined. "Test" is merely the name of the folder where the DE2_top resides. the DE2_top was take off of the DE2_examples cd.

Why is this? shouldn't this thing compile? It is the bare bones design. Every design I have worked on has been someone else's work.

What else do I need to do to get this basic thing to work right?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Sounds like you have an modified but incomplete version of the design DE2_TOP from the DE2 system CD.

    You should either go back to the original example design or look at your present one more thorougly. You didn't report the observation very clearly. What does the compiler exactly complain about?

    The project folder name as such doesn't matter. But all used verilog modules should be listed in the file list of your project, missing have to be added. The project is also defining a top entity, a module with this name must be present in one of the project's design files.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Alas the answer.

    I've been doing VHDL for about six months and forgot that it wasn't case sensitive. Verilog is. upon fixing that everything fell into place

    thanks