Cyclone 10, Passive Serial configuration Issues

Hi Eding,

Which Cyclone 10 family are you referring to? Is it Cyclone 10 LP or Cyclone 10 GX device? Since you mentioned the "there is nothing to distinguish Passive Serial and Passive Parallel on the MSEL inputs", I'm assuming you are referring to Cyclone 10 GX family devices. Cyclone 10 GX MSEL pins for PS and FPP modes are the same settings. Where else Cylone 10 LP MSEL pin settings are different between PS and FPP mode. Please do take note that Cyclone 10 family are architecture not the same as Cyclone V or even Cyclone IV family devices.

The Cyclone 10 GX configuration process is similar to the Arria 10 configuration process. The Cyclone 10 GX configuration control block will look for certain data pattern during the passive configuration process. These data patterns are used to decode the data width in the passive modes and to determine if encryption, authentication and compression are enabled. Theses data patterns are not disclose for public use. You can refer to the following KDB for further information on this:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd06052014_67.html

In general, the RBF files for PS and FPP mode are the same for any FPGA devices passive configuration process. Regardless if you set PS or FPP mode in Quartus, the output RBF files are the same. You can simply compare the RBF files and notice the data are exactly the same. Can you provide some screen shots the Quartus Device and Pin option settings and steps you did to generate the .rbf file?

You mentioned that you are using your own controller to perform the PS configuration. Did you follow the Cyclone 10 GX PS Configuration Timing Waveform and the PS Timing Parameters?

a. In Figure 145 "PS Configuration Timing Waveform" from the Cyclone 10GX handbook:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf

b. In Table 52 "PS Timing Parameters" from the Cyclone 10 GX datasheet:

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10gx-51002.pdf

Regards,

Nooraini