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I_like_leds_15's avatar
I_like_leds_15
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29 days ago
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Cyclone 10 LP Error Detection Timing

I am working with the cyclone 10 LP FPGA dev board from Altera.  I am trying to get the error detection block working during configuration. I have followed this guide: accessing-error-detection-bloc...
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  • Farabi's avatar
    Farabi
    24 days ago

    Hello, 

     

    The oscillator_divider generic does not change the CRC engine's clock. CRC is clocked by internal configuration oscillator. 

    Instead, set the clock in device option. 

    Device and Pin option -> Error Detection CRC -> "Divide error check frequency by"(this will impact the internal configuration oscillator that clocks the CRC engine. Valid values are power of 2. Below is the .qsf example :

     

    set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR <2|4|8|...|256>

     

    regards,

    Farabi