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Altera_Forum
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8 years ago

Cyclone 10 LP DDR IO-cell information

Where can we find the information on DDR operation of the IO-cells in Cyclone 10 LP?

The Intel® Cyclone® 10 LP Core Fabric and General Purpose I/O's Handbook only shows the SDR-mode (page 87)

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Are you going to use Cclone 10LP with own ddr I design?

    Cyclone 10 LP doesn't support DDR.

    DDR application/IP is only supported in C10 GX device.

    --- Quote End ---

    We would like to connect a DDR2 SDRAM, say at 166MHz.

    Yes, I read that somewhere else in the Cyclone 10 LP documentation as well.

    But you can find an HyperRAM device on own Intel's own cyclone 10 lp evaluation kitl (https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-lp-evaluation-kit.html), which, oh surprise, is a DDR device ...

    The ALTDDR_IN, ALTDDR_OUT and ALTDDR_IO primitives are supported by Quartus 17.1. The mapping is similar to what we find in Cyclone IV.

    So Intel chose to not to publish the technical details, why?

    The exercise is to get the 'lower cost' and 'lower power' but keep the Cyclone IV functionality. Or shall we buy ...

    This is for an entirely new design, which will last for years and many thousands ...

    Best regards,

    Josy
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    Any further information about this topic from Altera? We are in a similar position, considering the use of Cyclone 10 devices where previously Cyclone IV was used.

  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    --- Quote Start ---

    Any further information about this topic from Altera? We are in a similar position, considering the use of Cyclone 10 devices where previously Cyclone IV was used.

    --- Quote End ---

    No, and I don't think they are going to change their mind ...

    I have no idea about pricing (yet). If the pricing is good, I might consider developing our own DDR2 controller.
  • Altera_Forum's avatar
    Altera_Forum
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    7 years ago

    I re-compiled my test program for both Cyclone 10 LP and Cyclone IV E.

    You can see that the results are rather identical. 

    -- 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity scgige is
    port(
        Clk      : in    std_logic;
        DdrIn    : in    std_logic_vector(0 downto 0);
        SdrOut   : out   std_logic_vector(1 downto 0);
        DdrIO    : inout std_logic_vector(0 downto 0);
        SdrIOOut : out   std_logic_vector(1 downto 0);
        SdrIOIn : in    std_logic_vector(1 downto 0);
        DdrIOdir : in    std_logic
    );
end entity scgige;
architecture RTL of scgige is
    signal lsdrh : std_logic_vector(0 downto 0);
    signal lsdrl : std_logic_vector(0 downto 0);
    signal tddriodatainh : std_logic_vector(1-1 downto 0);
    signal tddriodatainl : std_logic_vector(1-1 downto 0);
    signal tddrio_DataOutH : std_logic_vector(1-1 downto 0);
    signal tddrio_DataOutL : std_logic_vector(1-1 downto 0);
begin
    tddrin : altddio_in
        generic map(
            width => 1
        )
        port map(
            aclr      => '0',
            aset      => '0',
            datain    => DdrIn,
            dataout_h => lsdrh,
            dataout_l => lsdrl,
            inclock   => Clk,
            inclocken => '1',
            sclr      => '0',
            sset      => '0'
        );
    process(Clk) is
    begin
        if rising_edge(Clk) then
            SdrOut <= (lsdrh(0) & lsdrl(0));
            SdrIOOut <= (tddrio_DataOutH(0) & tddrio_DataOutL(0));
            tddriodatainh(0) <= SdrIOIn(1);
            tddriodatainl(0) <= SdrIOIn(0);
        end if;
    end process;
    tddrio : altddio_bidir
        generic map(
            width                    => 1
        )
        port map(
            aclr            => '0',
            aset            => '0',
            combout         => open,
            datain_h        => tddriodatainh,
            datain_l        => tddriodatainl,
            dataout_h       => tddrio_DataOutH,
            dataout_l       => tddrio_DataOutL,
            dqsundelayedout => open,
            inclock         => Clk,
            inclocken       => '1',
            oe              => DdrIOdir,
            oe_out          => open,
            outclock        => Clk,
            outclocken      => '1',
            padio           => DdrIO,
            sclr            => '0',
            sset            => '0'
        );
end architecture RTL;