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That is not sufficient to synchronize to clk. The register for wr_d1 has a finite probability of becoming metastable when wr violates the register setup and hold time. You need at least one more register to reduce that probability, eg.
always_ff @ (posedge clk)
begin
wr_d1 <= wr;
wr_d2 <= wr_d1;
end
Since this code would be used multiple times, you should create a sync() component.
Dave
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Saw that suggestion in another thread. I actually have a double clocked register wr_d2 but I was wondering if its really that critical. I can use the second output.
Not sure what you mean by a sync component. I have similar syncing for wr, rd, and ale. Its in my main code. What is the advantage of putting it into a sync component?
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You probably don't want to use wr_d1 (or wr_d2) in this code, what you really want is an edge-detect of when wr_d2 goes from low-to-high. You can implement that logic using another delay, eg., wr_d3 <= wr_d2, and then wr_edge <= wr_d2 and !wr_d3; (if that is the right verilog symbol for not). Then use wr_edge in your opcode logic.
Cheers,
Dave
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I'm not quite sure how this would shift the edge 1/2 clk. When I code this I basically get the same as wr_d2 on wr_edge. I assume you meant something like:
assign wr_edge = (wr_d2 && !wr_d3);
or should I clock it into a register? (it does not seem to matter, other than it delays it one more cycle).
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