Clock problem

I found this piece of code which divides CLKIN to a fixed value.

Simply change the div := 2000000 assignment and renge to the value you need.

entity divider is
	port (CLKIN  : in  std_logic;  
			CLKOUT : out std_logic );
end entity divider; 
architecture divider_a of divider is
	subtype small_int is natural range 0 to 2000000;
	begin  
		update: process(CLKIN) is  
		variable div : small_int := 0;
		variable status : bit;
		begin
			if rising_edge(CLKIN) then  
				if div = 0 then
					div := 2000000;
					if status='0' then
						CLKOUT <= '1';
					else 
						CLKOUT <= '0';
					end if;
					status := not status;
				else
					div := div - 1;   
				end if;    
			end if;  
		end process;   
	end architecture divider_a;

Note: this was one of the very first things I made with VHDL.

Looking at it now I see some points which could have been implemented far better.:oops:

Anyway it worked and you can trust using it.