Check my layout

Hello,

I understand, that you have a two layer PCB with GND flooded top layer. Cause GND display is disabled, I can't see how this net is actual connected. Obviously GND connection can't be optimal, the same with supply bypass, but I wouldn't expect particular problems for the CPLD in this design. There may be a danger of double counts and timing violations with a ringing clock, but the said capacitor could help in this case.

TCK should have a pulldown (e. g. 10K), TDI and TMS may have pullups.

Regards,

Frank

Thanks

Found a missing ground. Updating artwork...

Adding pads for TCLK pulldown and TDI and TDS pullups. So, do I only need to install the pullups if the device won't program?

I have 150 ohm series resistors (R45 and R46) for protection on the programming pins to the 9S12 uP. Good idea or bad idea on the Altera? As Don Lancaster says "protect the protection."

New artwork:

http://www.jandssafeguard.com/topside.jpg

http://www.jandssafeguard.com/solderside.jpg

Hello,

displaying the flooded bottom layer, the ground connetion looks much better now. Regarding the pullups, the devicé would usually programm without them. Altera USB Blaster has e. g. 100k TCK pulldown, 100k TMS pullup and no TDI pullup. Possible issue is succeptibility to coupled switching noise, that may cause erroneous JTAG circuit behaviour. Thus the suitable resistance value depends on strength of interfering signals. If there isn't plenty of room for additional parts, I would provide a TCK pulldown as minimal means. Pullups at the other pins could possibly slightly reduce supply current.

Regards,

Frank

Frank:

I added the pads for three resistors as you advised.

Thanks again for your fine help.

John Pizzuto

J&S Electronics