Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy

Hi, 

1. The Agliex 7 F Series EMIF User Guide  page 191 Figure 145 of section 6.5.6.3 shows RESET line to DRAM pulled up to VDD with 4.7k ohm resistor and this was implemented on Agilex 7 F series evaluation board 

DDR4 memory vendor datasheet (thisis publicly available one for the MT40A2G8VA used on above linked eval board) states RESET must be low while power rails ramp up as pictured below which implies it should be instead pulled down to ground. 

Can Altera explain why they recommend pullup which seems to be opposite of what memory vendor specifies?

From above public Micron datasheet

2. Figure 143 in section 6.5.6.1 of Agilex 7 EMIF User Guide shows ADDR/CMD clock terminated to VDD through R and C network. 

Altera F Tile eval board  has ADDR/CMD clock terminated to GND through R and C network. Can Altera explain why the eval board implementation for this signal termination does not match the EMIF user guide figure 143 recommendation?

From Eval board

Thanks!