Forum Discussion

chandu_12867's avatar
chandu_12867
Icon for New Contributor rankNew Contributor
18 days ago

Agilex 5 A5ED043AB23AI2V with pcie and usb 3.1 design issue

Hi,

I took the design for the dev kit example design with the device (A5ED065BB32AE4SR0) for PCIe Gen4 x4 and HPS USB 3.1, and I changed the part number to A5ED043AB23AI2V and upgraded the required IPs and started the compilation. I am getting the error... I attached it. I thought this was due to the difference in package B32 vs. B23. For the B23 package, it only has 4c for PCIe and 1c for HPS USB 3.1. For B32, it has 4c and 4b banks also for PCIe and 1c for HPS USB 3.1. Does my part number support the req design with both PCIe Gen4 x4 and HPS USB 3.1? Because individually it is compiling; if not, why...? What is the reason...? If it supports where I am getting wrong. Please help me.

 

Thank you

 

 

 

3 Replies

  • VenT_Altera's avatar
    VenT_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 days ago

    Hi chandu_12867 

    Thank you for reaching out to us.  
    My apologies for the delayed response. I will review your questions regarding the PCIe IP.

    To better understand your issue, could you please provide the following details:

    1. Which dev kit are you using for the device with OPN: A5ED065BB32AE4SR0 (This is an ES device). Is this an Altera Dev Kit. Please share the Dev Kit link or user guide.
    2. What design example are you using for PCIe Gen4x4 and HPS USB3.1 combination? I am not aware of this design reference. Please share the link or the design example variant name.
    3. Quartus version used.
    4. If possible, please share the design.

     

    We need these details to further analyze the issue. Based on your description and the fitter errors, here are a few points to consider:

    • Moving from the B32A package to the B23A package reduces available resources and device density.
    • Moving from A5E065 to A5E043 reduces the GTS transceiver banks.
    • The fitter error indicates that the tool failed to place internal HPS nodes. When migrating from an ES device (or different OPN/package) to a production device, it is recommended to carefully upgrade the IP.
    • You may try regenerating the HPS IP from scratch for the B23A package (the production device) to avoid carrying over previous parameter settings.
    • To rule out any density limitations with the B23A package, you may also try compiling the same design with the B32A package again.

    Please let me know if you have any updates.

    Thanks. 
    Best Regards, 
    Ven 

    • chandu_12867's avatar
      chandu_12867
      Icon for New Contributor rankNew Contributor
      2 days ago

      Hi  VenT_Altera​  Thanks for reply 

      Altera agilex 5 premium development kit (I Think it is an engineering sample board).).

      link for the reference design : https://github.com/altera-fpga/agilex5-ed-pcie-rp/releases/download/25.1-2/a5ed065es-premium-devkit-pcie-rp-gen4x4.zip     

      We obtained the design from the above link and tried compiling it in Quartus Pro versions 25.1, 25.3, and 26.1  .

      i attached the design after changing the part number original design you can get from above link

      same reference design compiling in 065BB32 but we need in B23 package due to FPGA size must fit within our PCB constraints.

      Please let us know if there are any package-specific limitations or required modifications for supporting the B23 package.

      after extracting the zip while compiling if u get any .svh file not found error that is because of long path you just copy the file and paste in project folder where .qsf will be there and manually add it to project.