Nios II on the De0-Nano-SoC

Thanks for all the help everyone, I figured that was the case. Essentially in my final design, I don't intend to use a board with an HPS, since I'm not planning on using it. The amount of data I am storing on the FPGA is too big for the on chip memory of 64KB. I've connected the FPGA to the DDR3 via the F2SDRAM bridge, but I am having trouble getting the NIOS to connect to it, I am not really sure how to handle the addressing issues of connecting the data and instruction masters to the SDRAM bridge. Does anyone know of any examples of how to get this to work?