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MSteg2's avatar
MSteg2
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7 years ago

How to fix "OutOfMemoryError: Java heap space" error

We are building using the Quartus 11.1sp1 version (yes that is old but we have no reason to upgrade at this time)

I found where I can remove “DEAD” codespace by adding this to my Compiler options:

-fdata-sections -ffunction-sections

And also adding this to my LINK options:

--gc-section

For our Fast Fare this worked and my codespace is now smaller, but for our Fast Fare-e (which uses more RAM) I get the following ERROR.

On the “nios2-elf-g++” command to do the LINK:

OutOfMemoryError: Java heap space

make[3]: *** [farebox__fastfare-e__release.elf] Error 1

make[3]: *** Deleting file `farebox__fastfare-e__release.elf'

make[3]: Leaving directory `C:/altera/fastfare/software/app/farebox'

make[2]: *** [.gfi_elf] Error 2

make[2]: Leaving directory `C:/altera/fastfare/software/app/farebox'

make[1]: *** [.gfi_build] Error 2

make[1]: Leaving directory `C:/altera/fastfare/software/app/farebox'

make: *** [fastfare-e.release.gfi_build] Error 2

There is virtually no difference in these two builds and the code is 85% the same but there are bigger RAM buffers in Fast Fare-e due to a larger Display (so bigger Virtual GUI Buffers).

How do I fix this so I can remove DEAD CODE from the build??

For now I removed the options and I am building fine...

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  • MSteg2's avatar
    MSteg2
    Icon for New Contributor rankNew Contributor
    7 years ago

    We have an 8MB EPCS Flash and 16MB RAM and he RESET vector points to EPCS (BOOT).

    • Lower 1MB of this is FPGA and BOOT
    • Upper 7MB of this is our (zipped) APP ... which is built with SAME FPGA as BOOT (but does not have another copy)

    At Power Up:

    • The FPGA is loaded by H/W from EPCS Flash
    • The BOOT is copied into RAM and Vectored to in RAM by H/W
    • BOOT sees APP image in EPCS is VALID and unzips it to RAM and jumps to it (BOOT is now DONE)
    • APP image runs out of 16MB RAM (using FPGA loaded from BOOT)
  • Ahmed_H_Intel1's avatar
    Ahmed_H_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi,

    So if you are booting from the EPCS you can use the following:

    1- Use "small Hello wold template" which turns off all the unnecessary libraries

    2- Use optimization -O2 in the project settings.

    These two options will give you the smallest code size of your application. If you still facing the same error you can use the XIP "Execute In Place" to save more size of the RAM which won't copy the .text region of the code to RAM (If the EPCS can fit the design)

    In case if the EPCS cannot fit the design (FPGA+Zipped app) you can try:

    1. To configure the FPGA from another memory.
    2. Upgrade the EPCS flash. Configure the FPGA and Boot NIOS from EPCS with XIP on RAM.
    3. Upgrade the RAM and Configure the FPGA from EPCS and Run the NIOS on RAM.

    Otherwise I apologize if the design still out of memory, I have no clue to shrink it more than this to fit into the RAM and EPCS. Please let me know how can I help you.

    Regards,