Hi, I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this (http://www.alteraforum.com/forum/showthread.php?t=32354) and there's instructive information but it's a bit old and maybe there exist other ways. I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? Thanks for your help.

I believe you want the JTAG UART core on the FPGA end and software from Altera that talks to the NIOS on the PC end. http://www.altera.com/support/kdb/solutions/rd09142004_1190.html

--- Quote Start --- I have a DE0-nano board and I compute data (only 4 bits generated at about 10MHz) and I'd like to communicate it to the host cpu through the USB-blaster so programs could read it. I've read this and there's instructive information but it's a bit old and maybe there exist other ways. --- Quote End --- In addition to the JTAG UART, those are still the only ways you can transfer data :) http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial I haven't used the JTAG UART, but I think it suffers from the same problem the other interfaces do; no easy way to access the UART from user-provided software, eg., the JTAG UART does not show up as a COM port. --- Quote Start --- I thought about a FIFO that would be written by the FPGA then read by the host through the USB link. Is it possible? Have I to use a virtual JTAG component? --- Quote End --- The problem is, that the USB interface is not a general purpose USB interface. Its a USB-Blaster and it is "owned" by Quartus and jtagd. You can access it using FTDI's D2XX DLLs directly, but I'm not sure whether that "plays nicely" if you also happen to be using Altera's tools at the same time. The Wiki tutorial contains code for accessing the JTAG-to-Avalon-MM bridge via Altera's tools, and that is pretty much the only safe way to access the board via JTAG. It would be nice if Altera would publish their jtagd protocol, as then you'd be able to write sockets code to interact with jtagd, which would in turn interact with the JTAG interface on the FPGA (in a multi-process safe manner, since all communications is via jtagd). You could just buy an FTDI C232H cable and communicate with the board via that method. Cheers, Dave

Thanks Dave. I will carefully read everything... What I wonder is if it's easy to pass data from the console to the host programs (other than Altera) or maybe I should run them in the console. Is it possible? How? And as I don't care a communication from the host to the design (only from the design to the host), can't I use a simpler way of doing it?

--- Quote Start --- What I wonder is if it's easy to pass data from the console to the host programs (other than Altera) --- Quote End --- Altera do not provide a simple method for user-coded software to interface to their USB-Blaster components, i.e., what you would like is a shared library you could call into that would play nicely with simultaneous operation of SystemConsole, SignalTap II, and other Quartus software. --- Quote Start --- or maybe I should run them in the console. Is it possible? How? And as I don't care a communication from the host to the design (only from the design to the host), can't I use a simpler way of doing it? --- Quote End --- The solutions I show in the tutorial above involve running a server in SystemConsole, and then using a TCP/IP connection from your custom code. If you do not care about running Altera's software in parallel with your code, you can use the FTDI driver to access the USB-Blaster directly. Although that involves decoding Altera's custom (and undocumented) protocols. Cheers, Dave

--- Quote Start --- (only 4 bits generated at about 10MHz) --- Quote End --- For what it's worth, you might get to your end goal faster (cheaper) by using something like FTDI UM232H module if your DE0-nano header pins aren't already used up. Configured for parallel FIFO operation, there should be ample throughput to sustain the 40Mbps you're generating. http://www.ftdichip.com/support/documents/datasheets/modules/ds_um232h.pdf http://www.digikey.com/product-detail/en/um232h/768-1103-nd/2614628

Data from FPGA to host | Altera Community

85 Replies

Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Yes I will take the time to learn but I don't understand everything.

--- Quote End ---

Neither do I :)

--- Quote Start ---

Please tell me what a BFM is exactly.

--- Quote End ---

A BFM is a bus functional model. Its a simulation-only component that allows you to generate standardized bus transactions, eg., Avalon-MM master transactions in this case.

--- Quote Start ---

And tell me what I should do (generate VHDL simulation files, create a simulation environment, look with Signaltap at what the stimulus should be...)
--- Quote End ---

Sorry, only you can do that, its your project.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Sorry, only you can do that, its your project.

--- Quote End ---

That's not what I wanted to say.
I just wanted to know IF I have to write all that.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
That's not what I wanted to say.
I just wanted to know IF I have to write all that.
--- Quote End ---

Yes, all projects should have the synthesizeable HDL code, a simulation for that code (or at least the custom components used by that code, eg., custom Avalon-MM slaves), and hardware verification.

Without these components, you have not really "designed" and "verified" anything.

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Now I still have problems configuring SignalTap II:
as stated in posts# 54 to# 57 I can't see the "first" edge of the trigger, even when waiting for a long time after starting the acquisition and before starting the process. Surely my configuration is bad but I can't find the problem.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
Now I still have problems configuring SignalTap II:
as stated in posts# 54 to# 57 I can't see the "first" edge of the trigger, even when waiting for a long time after starting the acquisition and before starting the process. Surely my configuration is bad but I can't find the problem.
--- Quote End ---

Try a different solution then.

For example. Rather than trigger off your asynchronous signal, trigger off a counter inside the FPGA. Have that counter enabled by your external signal, but first make sure that external signal is synchronized to the clock used by SignalTap II and the counter. Then trigger off the counter, eg., a count of 1.

Doing this may make you realize what you were doing wrong earlier.

Cheers,
Dave

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Data from FPGA to host

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